This invention relates to semiconductor electronic devices, and, more particularly, to stacked CMOS devices.
Complementary MOS (CMOS) logic is an important and well known semiconductor technology; CMOS consumes less stand-by power than any other MOS logic configuration. However, this advantage is gained at the expense of substrate area per logic unit. Thus many efforts have been made to increase the packing density of CMOS devices, including the scaling down of device dimensions, and the stacking of devices to save substrate area.
The scaling down of device dimensions cannot be made arbitrarily; rather, scaling rules apply in order to preserve device characteristics. For example, the channel length to width ratio is proportional to the resistive impedance of a MOS device. See, for example, Mead and Conway, Introduction to VLSI Systems (1980) and Enomoto et al, Design Fabrication and Performance of Scaled Analog IC's, IEEE Journal of Solid-State Circuits, Vol. SC-18, pp 395-402 (1983).
Another way of increasing the density of devices on a substrate on constant area would be to stack active layers upon each other and build devices into them. Recent technqiues of laser recrystallizing polysilicon have allowed the fabrication of stacked CMOS devices using a common gate. Such devices are basically fabricated by depositing n-type polysilicon over a standard n-channel device, laser recrystallizing the polysilicon near and overlying the gate of the n-channel device, followed by p+ source/drain doping in the polysilicon to form a p-channel device controlled by the same gate as the n-channel device. See, for example, Colinge et al, Stacked Transistor CMOS (ST-MOS) and NMOS Technology Modified to CMOS, IEEE Journal Solid-State Circuits, Vol. SC-17, pp. 215-219 (1982). Due to the vertical stacking of such devices, such circuits are potentially denser by about a factor of two. Also, there is no parasitic pnpn structure such as one finds in conventional bulk CMOS, and stack CMOS circuits are free of latchup problems.
Nevertheless, when such stacked CMOS circuits are scaled down, the alignment of the channel of the overlying polysilicon p-channel device becomes a problem. In particular, the underlying n-channel is normally fabricated by first forming the gate poly and then diffusing the source and drain regions with the gate acting as a mask; this yields a self-aligned device. For the overlying p-channel polysilicon device, however, the gate is underneath the polysilicon and cannot be used as a mask when the source and drain are being diffused. Thus the alignment of a photolithographic mask becomes crucial. For example, if the overlying p-channel device is to have a channel length of L and the error in mask alignment is S, then the gate must be of width at least L+2S to insure the channel of the p-channel device being entirely over the gate. However, if the gate has a width of L+2S then the self-aligned n-channel device will have a channel length of L+2S neglecting small lateral diffusion underneath the gate. And as the device dimensions are scaled down the error in mask alignment may almost eliminate the saving from stacking. Indeed, if the channel length L were to be 1.0 microns and the mask alignment error S were 0.5 microns then the n-channel length would be 2 microns; i.e. twice as long as desired. Further, the width of the n-channel would be twice as wide as desired to maintain the same length to width ratio. In effect, the n-channel would occupy four times as much area as desired.
Attempts to solve this alignment problem for stacked CMOS have been made. For example, A. L. Robinson et al, A Fully-Self-Aligned Joint-Gate CMOS Technology, IEDM Technical Digest, pp. 530-533, 1983, claims, a process, but the processing steps are not simple and the solution is not all together satisfactory since in scaling the device down the bulk silicon device is still a problem because a lithographic step is used on top the stack to pattern and then etch the source and drain extensions. The limitations imposed by the lithographic step are entirely similar to the other non-self-aligned approach discussed above.
Thus, it is a problem with the prior art to scale down stacked CMOS devices while substantially retaining the savings in the substrate area as the feature size approaches the patterning alignment error.